This invention relates to an imaging chargecoupled device (CCD) having an all parallel output.
One form of imaging CCD comprises a silicon die which has been processed using conventional MOS technology to form a plurality of buried channels beneath its front surface (the surface through which the die is processed). Each channel is made up of a linear array of like elementary regions. A clocking electrode structure overlies the front surface of the die, and by application of selected potentials to the clocking electrode structure, charge present in a given elementary region of a channel may be advanced through the linear array of elementary regions, in the manner of a shift register, and extracted from the channel. In an imaging CCD, charges are generated in the channels photoelectrically. Thus, if electromagnetic radiation is incident on the substrate beneath the channel layer it may cause generation of conduction electrons and these conduction electrons may enter the channel layer and become confined in one of the elementary channel regions. The diffusion length of the conduction electrons is sufficiently short that a conduction electron generated in the substrate will not pass by diffusion farther than the elementary channel region that immediately overlies the substrate region in which the conduction electron was generated.
The imaging CCD is placed with the back surface of the die at the focal plane of a camera so that the camera lens forms an image of a scene on the back surface of the die. The CCD may comprise, e.g., 64 parallel channels each having 64 elementary regions and the resulting 64.times.64 array of elementary regions resolves the back, or image receiving, surface of the die into 64.times.64 picture elements or pixels. The camera has a shutter which is opened for a predetermined exposure interval, during which all electrodes of the clocking electrode structure remain at constant potentials. The shutter is then closed, and the charge accumulated in the elementary channel regions is clocked out of the CCD. The intensity of the optical energy incident on a given pixel during the exposure interval can influence the electron population of the associated elementary region of the channel layer, and so the number of electrons that are transferred out of an elementary region, and ultimately extracted from the CCD, is representative of the intensity of the light incident on the pixel. In this manner, the CCD can be used to generate a two-dimensionally sampled electrical signal representative of the distribution of light intensity over the image receiving surface of the CCD, i.e. of the image formed by the camera lens.
In a known imaging CCD having 64 parallel channels, the pixel charge samples are clocked out of the channels into a parallel in, serial out shift register and are shifted through the shift register to a floating diffusion, which is electrically coupled to the gate electrode of an output field-effect transistor. The voltage at the source electrode of the output FET depends on the voltage at the gate electrode. In order to prevent the voltage at the gate electrode of the output FET from being influenced by pixel charge samples that have previously been applied to the floating diffusion, a reset gate is used to reset the floating diffusion to a reference potential at a predetermined time after each pixel sample charge has been deposited in the floating diffusion. Thus, the floating diffusion is spaced from an output diffusion, and a reset gate lies over a channel region defined between the floating diffusion and the output diffusion. When an appropriate potential is applied to the reset gate, charge is able to flow through the channel region between the output diffusion and the floating diffusion and the floating diffusion is brought to the same potential as the output diffusion.
If the pixel charge samples are shifted through the columns of the CCD at a frequency f.sub.c and the CCD has 64 columns, the rate at which pixel charge samples are shifted out of the shift register is 64 f.sub.c. Therefore, the rate at which pixel charge samples can be shifted out of the shift register imposes a limit on f.sub.c.
In order to maximize f.sub.c, it has been proposed that each channel of the imaging CCD should have its own floating diffusion, connected by a floating diffusion bus to the gate electrode of its own output FET, so that the CCD provides an all parallel output. The source electrodes of the output FETs may then be applied through suitable amplification and other circuits to a parallel processing computer. In this fashion, the rate at which pixel charge samples are shifted through the channels of the CCD is made independent of the number of columns.
A difficulty that has been encountered with such an all parallel output imaging CCD is that it is necessary to provide a reset bus which is connected to the reset gates. If the reset bus passes over the surface of the CCD at a location between the floating diffusions and the gate electrodes of the output FETs, the reset bus is strongly coupled to the floating diffusion buses. When a reset pulse is applied to the reset bus, noise is introduced on the floating diffusion buses and influences the voltage detected at the source electrodes of the output FETs.